Technical Document
Specifications
Brand
NexperiaLogic Function
Inverter
Input Type
Schmitt Trigger
Number of Elements per Chip
2
Schmitt Trigger Input
Yes
Maximum Propagation Delay Time @ Maximum CL
12 ns @ 50 pF
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Mounting Type
Surface Mount
Package Type
SC-88
Pin Count
6
Logic Family
LVC
Dimensions
2.2 x 1.35 x 1mm
Maximum Operating Supply Voltage
5.5 V
Height
1mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Length
2.2mm
Width
1.35mm
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
50pF
Product details
74LVC Family Inverters & Buffers
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
74LVC Family
€ 15.60
€ 0.39 Each (In a Pack of 40) (ex VAT)
€ 18.56
€ 0.464 Each (In a Pack of 40) (inc. VAT)
Standard
40
€ 15.60
€ 0.39 Each (In a Pack of 40) (ex VAT)
€ 18.56
€ 0.464 Each (In a Pack of 40) (inc. VAT)
Standard
40
Stock information temporarily unavailable.
Please check again later.
quantity | Unit price | Per Pack |
---|---|---|
40 - 40 | € 0.39 | € 15.60 |
80 - 160 | € 0.29 | € 11.60 |
200 - 360 | € 0.23 | € 9.20 |
400 - 760 | € 0.21 | € 8.40 |
800+ | € 0.18 | € 7.20 |
Technical Document
Specifications
Brand
NexperiaLogic Function
Inverter
Input Type
Schmitt Trigger
Number of Elements per Chip
2
Schmitt Trigger Input
Yes
Maximum Propagation Delay Time @ Maximum CL
12 ns @ 50 pF
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Mounting Type
Surface Mount
Package Type
SC-88
Pin Count
6
Logic Family
LVC
Dimensions
2.2 x 1.35 x 1mm
Maximum Operating Supply Voltage
5.5 V
Height
1mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Length
2.2mm
Width
1.35mm
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
50pF
Product details
74LVC Family Inverters & Buffers
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS