Technical Document
Specifications
Brand
NexperiaLogic Function
Inverter Schmitt Trigger
Input Type
Schmitt Trigger
Output Type
Single Ended
Number of Elements per Chip
2
Schmitt Trigger Input
Yes
Maximum Propagation Delay Time @ Maximum CL
14.7 ns @ 30 pF
Maximum High Level Output Current
-24mA
Maximum Low Level Output Current
24mA
Mounting Type
Surface Mount
Package Type
TSSOP
Pin Count
14
Logic Family
74LVC
Dimensions
5.1 x 4.5 x 0.95mm
Height
0.95mm
Maximum Operating Supply Voltage
3.6 V
Width
4.5mm
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Temperature
+125 °C
Propagation Delay Test Condition
30pF
Length
5.1mm
Product details
74LVC Family Inverters & Buffers
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
74LVC Family
Stock information temporarily unavailable.
Please check again later.
€ 0.33
Each (In a Pack of 100) (ex VAT)
€ 0.393
Each (In a Pack of 100) (inc. VAT)
Standard
100
€ 0.33
Each (In a Pack of 100) (ex VAT)
€ 0.393
Each (In a Pack of 100) (inc. VAT)
Standard
100
Buy in bulk
quantity | Unit price | Per Pack |
---|---|---|
100 - 1200 | € 0.33 | € 33.00 |
1300+ | € 0.28 | € 28.00 |
Technical Document
Specifications
Brand
NexperiaLogic Function
Inverter Schmitt Trigger
Input Type
Schmitt Trigger
Output Type
Single Ended
Number of Elements per Chip
2
Schmitt Trigger Input
Yes
Maximum Propagation Delay Time @ Maximum CL
14.7 ns @ 30 pF
Maximum High Level Output Current
-24mA
Maximum Low Level Output Current
24mA
Mounting Type
Surface Mount
Package Type
TSSOP
Pin Count
14
Logic Family
74LVC
Dimensions
5.1 x 4.5 x 0.95mm
Height
0.95mm
Maximum Operating Supply Voltage
3.6 V
Width
4.5mm
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Temperature
+125 °C
Propagation Delay Test Condition
30pF
Length
5.1mm
Product details
74LVC Family Inverters & Buffers
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS